1. Field
The present disclosure pertains to the field of processors. More particularly, the present disclosure pertains to branch ordering logic that may be used to assist in branch mispredict recovery in a speculative execution, out-of-order processor.
2. Description of Related Art
Improving the performance of computer or other processing systems generally improves overall throughput and/or provides a better user experience. Such improved computer or other processing system performance may be achieved by increasing the rate at which instructions for the system are processed by a processor. Accordingly, it is desirable to produce advanced processors with improved instruction throughput.
Continuing to increase the performance of a processor, however, is a difficult task. Prior art and processors already employ techniques of branch prediction, speculative execution, and out-of-order (OOO) execution. Speculative execution allows conditional branches to be predicted rather than awaiting computation of the condition. In general, the branch prediction is usually correct and therefore the speculation improves performance. When branch mispredicts occur, however, the results of the incorrect speculation must be undone.
One technique of undoing or xe2x80x9cunwindingxe2x80x9d mistakes (i.e., mispredicted branches) is described in U.S. Pat. No. 5,586,278 (the ""278 patent). The processor described by the ""278 patent uses a separate retirement register file (RRF) to maintain the committed architectural register state of the processor. Thus, changes in register values are not committed to the RRF until branch predictions are resolved.
Accordingly, in a processor such as that described in the ""278 patent, the committed state of registers does not reflect the results of any branches unless they are known to have been properly predicted. While the use of such a separate register file may have its advantages, it may disadvantageously require register values to be copied from a set of renamed registers to the retirement register file upon instruction retirement. In some cases, this type of register value transfer may be a disadvantageously time consuming operation. Furthermore, such prior art processors may rely on flushing all or large portions of the processor pipeline upon mispredicts.
As more complicated, faster, or otherwise different speculating OOO processor architectures evolve, there is a continuing need for logic which facilitates rapid recovery from mispredicted branches without unduly slowing other operations.